1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, and more particularly, to the structure of an SRAM and manufacturing method thereof.
2. Background Art
With an increase in the degree of integration of a semiconductor device, the size of a semiconductor memory represented by SRAM (Static Random Access Memory) or the like is becoming smaller. In line with this, the size and wiring pitch of elements mounted in the semiconductor memory are becoming smaller.
In Japanese Unexamined Patent Publication No. 10-178110, a layout for reducing a cell area of an SRAM made up of CMOS devices whose one bit consists of 6 transistors is disclosed.
FIG. 17 shows a general layout of the above described SRAM. This figure shows a memory corresponding to one bit of the SRAM. Each element is disposed so as to be symmetric with respect to a center point E.
Active regions 1a to 1d are provided inside a memory cell region C. A gate 2a is disposed so as to cross the active region 1a and a gate 2b is disposed so as to cross the active regions 1a, 1b. A shared contact (hereinafter referred to as “SC”) 3 is provided so as to connect the active region 1b and gate 2c. The gate 2a is provided with a contact 4a. The active region 1a is provided with contacts 4b, 4c and 4d. The active region 1b is provided with a contact 4e. Metal wirings 5b, 5c, 5d and 5e are provided so as to cover the contacts 4b, 4c, 4d and 4e respectively. The active region 1a is connected to the active region 1b through the contact 4c, metal wiring 5b and SC3. The active region 1b is connected to the gate 2c through the SC3.
In the above described semiconductor device, the contact 4c is disposed between the gate 2a and gate 2b. For this reason, it is difficult to shorten a distance t1 between the gate 2a and gate 2b. 